1. Field
Exemplary embodiments of the present invention relate to a method for fabricating a semiconductor device, and more particularly, to a semiconductor device with a damascene bit line and a method for fabricating the same.
2. Description of the Related Art
Recently, with the increase in integration degree of semiconductor devices, the difficulty level of a self-aligned contact (SAC) process has rapidly increased. The SAC process is performed for a storage node contact (SNC) plug after a bit line with a stacked structure is formed. In sub-30 nm memory devices, it may be difficult to secure an open area of an SNC hole and a SAC fail may frequently occur, due to such a reduction in process margin.
In order to solve such features, a damascene bit line process has been proposed. In the damascene bit line process, an SNC plug is first formed, and a bit line is subsequently formed.
In the damascene bit line process, two SNC plugs adjacent to each other are formed at once, and then separated from each other through a damascene process. Then, a bit line is formed to fill the inside of the damascene pattern. Through such a process, the SNC plugs may be more easily patterned than when the SNC plugs are separately formed. Furthermore, this process has an advantage in terms of the SAC fail, compared with a process in which the SNC plugs are formed later.
In the damascene bit line process, a spacer may be formed on the sidewalls of the bit line, in order to prevent the bit line and the SNC plugs from being short-circuited.
The spacer may be formed of a dielectric layer such as silicon nitride or the like. Since the silicon nitride has a high dielectric constant, the silicon nitride may not be effective in suppressing parasitic capacitance between the bit line and the SNC plugs.